The present invention relates generally to a process for manufacturing a thin film transistor, and, more particularly, to a process for manufacturing an offset gate structure thin film transistor.
A thin film transistor (TFT) is typically employed as a load resistor of a memory cell in a static random access memory device (SRAM), as a switching device for supplying a voltage to a pixel in a liquid crystal display device (LCD), and as a driving device for driving the peripheral circuits in an LCD. When used as a switching device in an LCD, the channel of the TFT is connected between a data line to which a driving voltage is supplied, and a pixel electrode, which applies the driving voltage to the liquid crystal of the LCD, and the gate electrode of the TFT is connected to a scan line to which a scanning signal is applied.
Such a TFT switching device for an LCD is generally fabricated in silicon. Typically, such a TFT includes a polysilicon or amorphous silicon active layer formed or stacked on the surface of a transparent substrate, such as a glass or quartz substrate, of the LCD, and a gate electrode deposited on a central portion of a gate insulating layer formed on the upper surface of the active layer. During fabrication, the source and drain regions are formed in the active layer by means of a well-known ion-implanation process, using the gate electrode as a self-alignment mask, such as is disclosed in U.S. Pat. No. 4,597,160. However, such a technique has a drawback, in that the channel region of the device (i.e., the region of the active layer beneath the gate electrode) is adjacent to the source and drain regions, thus increasing the off current of the device. By "off current", is meant the leakage current which flows between the source and drain electrodes of the device due to the electric field formed between the drain (or source) electrode and the gate electrode when no voltage is applied to the gate electrode, i.e., the applied gate (scan) voltage signal is "low" or "off". The charge that is accumulated due to the leakage current flowing from the source electrode, which is coupled to the pixel electrode, to the drain electrode, through the channel region, is leaked to the data line which is coupled to the drain electrode, which obviously has a deleterious effect on the performance and reliability of the device.
In order to overcome the above-described drawback of the conventional TFT fabrication technique, there has been proposed a TFT having an offset gate structure, in which the channel region is separated from the source and drain regions by respective offset resistance regions formed in opposite side portions of the channel region. More particularly, with reference now to FIG. 1, such an offset gate structure TFT includes an active layer 2 formed on the surface of a transparent substrate (not shown), a gate insulating layer 4 formed on a central portion of the upper surface of the active layer 2, and a gate electrode 6 formed on the gate insulating film 4. During fabrication, a photomask (not shown) is formed on the resultant structure and then etched by a photolithographic process so that the resultant patterned photomask covers the gate structure (4,6) and opposite side portions 2a-1, 2a-2 of the channel region 2a of the active layer 2. Then, the source and drain regions 2b, 2c, respectively, of the TFT are formed by an ion-implantation process, using the patterned photomask as an ion-implantation mask. Subsequently, the patterned photomask is removed.
Because the side portions 2a-1, 2a-2 of the channel region 2 remain undoped, they serve as offset resistance regions between the channel region 2 and the source region 2b, and between the channel region 2 and the drain region 2c, respectively, to thereby reduce the off current of the device. However, although such an offset gate structure TFT overcomes the excessive off current problem of the conventional TFT technology, the manufacture thereof requires additional photolithographic steps (deposition, patterning, and removal of ion-implantation photomask) which increase the complexity and expense of the TFT manufacturing process.
Further, it is well-known in the art that the thinner the active layer is, the greater the on current and the less the off current, thereby enhancing the performance of the TFT. However, because the overlying gate structure of the TFT is extremely thin, if the active layer is formed to a thickness of less than about 1,000 angstroms, major reliability and performance problems due to over-etching during the metal contact etching process occur. Thus, the currently available TFT manufacturing technology is limited in this respect.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a process for manufacturing an offset gate structure TFT which overcomes the above-described drawbacks and shortcomings of the presently available TFT manufacturing technology. The present invention fulfills this need.